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| author | Andrew Jeffery | 2021-03-09 12:01:28 +0100 |
|---|---|---|
| committer | Cédric Le Goater | 2021-03-09 12:01:28 +0100 |
| commit | 957ad79f7316816433f772b1a9ebdfe0a3818cb2 (patch) | |
| tree | 180b8f99a418d0301bb19be759cbe87cb9d4bd40 /hw/arm | |
| parent | hw/arm/aspeed: Fix location of firmware images in documentation (diff) | |
| download | qemu-957ad79f7316816433f772b1a9ebdfe0a3818cb2.tar.gz qemu-957ad79f7316816433f772b1a9ebdfe0a3818cb2.tar.xz qemu-957ad79f7316816433f772b1a9ebdfe0a3818cb2.zip | |
hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC
This appears to be a requirement of the GIC model. The AST2600 allocates
197 GIC IRQs, which we will adjust shortly.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210302014317.915120-2-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/aspeed_ast2600.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 49b0076386..3d9e78fcc6 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -65,7 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { #define ASPEED_A7MPCORE_ADDR 0x40460000 -#define ASPEED_SOC_AST2600_MAX_IRQ 128 +#define AST2600_MAX_IRQ 128 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ static const int aspeed_soc_ast2600_irqmap[] = { @@ -260,7 +260,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, &error_abort); object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", - ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, + ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); |