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author | Peter Maydell | 2020-11-10 10:24:56 +0100 |
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committer | Peter Maydell | 2020-11-10 10:24:56 +0100 |
commit | f7e1914adad8885a5d4c70239ab90d901ed97e9f (patch) | |
tree | e117402b27c20ce664ca2ee01023d271d272c438 /hw/arm | |
parent | Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2020-11-09-tag' in... (diff) | |
parent | hw/intc/ibex_plic: Clear the claim register when read (diff) | |
download | qemu-f7e1914adad8885a5d4c70239ab90d901ed97e9f.tar.gz qemu-f7e1914adad8885a5d4c70239ab90d901ed97e9f.tar.xz qemu-f7e1914adad8885a5d4c70239ab90d901ed97e9f.zip |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging
This fixes two bugs in the RISC-V port. One is a bug in the
Ibex PLIC, the other fixes the Hypvervisor access functions.
# gpg: Signature made Tue 10 Nov 2020 03:53:49 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20201109:
hw/intc/ibex_plic: Clear the claim register when read
target/riscv: Split the Hypervisor execute load helpers
target/riscv: Remove the hyp load and store functions
target/riscv: Remove the HS_TWO_STAGE flag
target/riscv: Set the virtualised MMU mode when doing hyp accesses
target/riscv: Add a virtualised MMU Mode
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm')
0 files changed, 0 insertions, 0 deletions