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| author | Peter Maydell | 2012-03-14 16:37:53 +0100 |
|---|---|---|
| committer | Peter Maydell | 2012-03-16 19:09:55 +0100 |
| commit | 0e4a398ab2c5e9b540a80859ec28163b65e7a891 (patch) | |
| tree | d82d2b3d85816bce616ec40325ebd49be3de9c6b /hw/arm_gic.c | |
| parent | hw/omap_i2c: Convert to qdev (diff) | |
| download | qemu-0e4a398ab2c5e9b540a80859ec28163b65e7a891.tar.gz qemu-0e4a398ab2c5e9b540a80859ec28163b65e7a891.tar.xz qemu-0e4a398ab2c5e9b540a80859ec28163b65e7a891.zip | |
ARM: Remove unnecessary subpage workarounds
In the ARM per-CPU peripherals (GIC, private timers, SCU, etc),
remove workarounds for subpage memory region read/write functions
being passed offsets from the start of the page rather than the
start of the region. Following commit 5312bd8b3 the masking off
of high bits of the address offset is now harmless but unnecessary.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'hw/arm_gic.c')
| -rw-r--r-- | hw/arm_gic.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/arm_gic.c b/hw/arm_gic.c index d8a7a190e8..6b34c06a8f 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -658,14 +658,14 @@ static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr, unsigned size) { gic_state *s = (gic_state *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(), addr & 0xff); + return gic_cpu_read(s, gic_get_current_cpu(), addr); } static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr, uint64_t value, unsigned size) { gic_state *s = (gic_state *)opaque; - gic_cpu_write(s, gic_get_current_cpu(), addr & 0xff, value); + gic_cpu_write(s, gic_get_current_cpu(), addr, value); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -677,7 +677,7 @@ static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr, gic_state **backref = (gic_state **)opaque; gic_state *s = *backref; int id = (backref - s->backref); - return gic_cpu_read(s, id, addr & 0xff); + return gic_cpu_read(s, id, addr); } static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, @@ -686,7 +686,7 @@ static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, gic_state **backref = (gic_state **)opaque; gic_state *s = *backref; int id = (backref - s->backref); - gic_cpu_write(s, id, addr & 0xff, value); + gic_cpu_write(s, id, addr, value); } static const MemoryRegionOps gic_thiscpu_ops = { |