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| author | pbrook | 2006-04-09 03:32:52 +0200 |
|---|---|---|
| committer | pbrook | 2006-04-09 03:32:52 +0200 |
| commit | cdbdb648b7c2867f0bb7dce27efb1986f770dedb (patch) | |
| tree | f838b39e8f30e4872a792638e532d8ac8db6fbfc /hw/arm_pic.h | |
| parent | Allow multiple graphics devices. (diff) | |
| download | qemu-cdbdb648b7c2867f0bb7dce27efb1986f770dedb.tar.gz qemu-cdbdb648b7c2867f0bb7dce27efb1986f770dedb.tar.xz qemu-cdbdb648b7c2867f0bb7dce27efb1986f770dedb.zip | |
ARM Versatile Platform Baseboard emulation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1804 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/arm_pic.h')
| -rw-r--r-- | hw/arm_pic.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/hw/arm_pic.h b/hw/arm_pic.h new file mode 100644 index 0000000000..b29914985a --- /dev/null +++ b/hw/arm_pic.h @@ -0,0 +1,27 @@ +/* + * Generic ARM Programmable Interrupt Controller support. + * + * Copyright (c) 2006 CodeSourcery. + * Written by Paul Brook + * + * This code is licenced under the LGPL. + * + * Arm hardware uses a wide variety of interrupt handling hardware. + * This provides a generic framework for connecting interrupt sources and + * inputs. + */ + +#ifndef ARM_INTERRUPT_H +#define ARM_INTERRUPT_H 1 + +/* The first element of an individual PIC state structures should + be a pointer to the handler routine. */ +typedef void (*arm_pic_handler)(void *opaque, int irq, int level); + +/* The CPU is also modeled as an interrupt controller. */ +#define ARM_PIC_CPU_IRQ 0 +#define ARM_PIC_CPU_FIQ 1 +void *arm_pic_init_cpu(CPUState *env); + +#endif /* !ARM_INTERRUPT_H */ + |