diff options
| author | Anup Patel | 2022-02-04 18:46:54 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-02-16 03:24:19 +0100 |
| commit | e8f79343cfc886aaa225cec9faf6881f75945209 (patch) | |
| tree | 9635d35329eb2f05cd58d22484a06e8b291696c0 /hw/core/cpu-sysemu.c | |
| parent | target/riscv: Allow users to force enable AIA CSRs in HART (diff) | |
| download | qemu-e8f79343cfc886aaa225cec9faf6881f75945209.tar.gz qemu-e8f79343cfc886aaa225cec9faf6881f75945209.tar.xz qemu-e8f79343cfc886aaa225cec9faf6881f75945209.zip | |
hw/intc: Add RISC-V AIA APLIC device emulation
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for wired interrupts called APLIC (Advanced
Platform Level Interrupt Controller). The APLIC is capabable of
forwarding wired interupts to RISC-V HARTs directly or as MSIs
(Message Signaled Interupts).
This patch adds device emulation for RISC-V AIA APLIC.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-19-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/core/cpu-sysemu.c')
0 files changed, 0 insertions, 0 deletions