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authorPhilippe Mathieu-Daudé2019-07-15 15:17:03 +0200
committerPeter Maydell2019-07-15 15:17:03 +0200
commit526668c734e6a07f2fedfd378840a61b70c1cbab (patch)
tree705d632e1901ec42eaf84d7f12be26f46ec15996 /hw/core/loader.c
parenthw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory (diff)
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hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
Both lqspi_read() and lqspi_load_cache() expect a 32-bit aligned address. >From UG1085 datasheet [*] chapter on 'Quad-SPI Controller': Transfer Size Limitations Because of the 32-bit wide TX, RX, and generic FIFO, all APB/AXI transfers must be an integer multiple of 4-bytes. Shorter transfers are not possible. Set MemoryRegionOps.impl values to force 32-bit accesses, this way we are sure we do not access the lqspi_buf[] array out of bound. [*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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