diff options
author | Alexander Graf | 2013-12-11 14:17:44 +0100 |
---|---|---|
committer | Alexander Graf | 2013-12-20 01:58:03 +0100 |
commit | 582b55a96ac4f66cea64d82e47651bd5ef38a8ec (patch) | |
tree | abcae368c4aa57f047e23b76fb9bd25a19a33bcc /hw/core/loader.c | |
parent | spapr: tie spapr-nvram to -pflash (diff) | |
download | qemu-582b55a96ac4f66cea64d82e47651bd5ef38a8ec.tar.gz qemu-582b55a96ac4f66cea64d82e47651bd5ef38a8ec.tar.xz qemu-582b55a96ac4f66cea64d82e47651bd5ef38a8ec.zip |
roms: Flush icache when writing roms to guest memory
We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're basically emulating the cache
off phase on very early system bootup.
That phase is usually responsible for clearing the instruction cache for
anything it writes into cachable memory, to ensure that after reboot we
don't happen to execute stale bits from the instruction cache.
So we need to invalidate the icache every time we write a rom into guest
address space. We do not need to do this for every DMA since the guest
expects it has to flush the icache manually in that case.
This fixes random reboot issues on e5500 (booke ppc) for me.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/core/loader.c')
-rw-r--r-- | hw/core/loader.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/hw/core/loader.c b/hw/core/loader.c index 60d2ebd4ac..0634bee20c 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -785,6 +785,13 @@ static void rom_reset(void *unused) g_free(rom->data); rom->data = NULL; } + /* + * The rom loader is really on the same level as firmware in the guest + * shadowing a ROM into RAM. Such a shadowing mechanism needs to ensure + * that the instruction cache for that new region is clear, so that the + * CPU definitely fetches its instructions from the just written data. + */ + cpu_flush_icache_range(rom->addr, rom->datasize); } } |