summaryrefslogtreecommitdiffstats
path: root/hw/core/machine.c
diff options
context:
space:
mode:
authorPeter Maydell2018-06-29 18:17:31 +0200
committerRichard Henderson2018-07-02 17:02:20 +0200
commit4b1a3e1e34ad971b58783d4a24448ccbf5bd8fd4 (patch)
tree390aa187f375330343f979aaeb485754e9eecf64 /hw/core/machine.c
parentaccel/tcg: Correct "is this a TLB miss" check in get_page_addr_code() (diff)
downloadqemu-4b1a3e1e34ad971b58783d4a24448ccbf5bd8fd4.tar.gz
qemu-4b1a3e1e34ad971b58783d4a24448ccbf5bd8fd4.tar.xz
qemu-4b1a3e1e34ad971b58783d4a24448ccbf5bd8fd4.zip
accel/tcg: Don't treat invalid TLB entries as needing recheck
In get_page_addr_code() when we check whether the TLB entry is marked as TLB_RECHECK, we should not go down that code path if the TLB entry is not valid at all (ie the TLB_INVALID bit is set). Tested-by: Laurent Vivier <laurent@vivier.eu> Reported-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180629161731.16239-1-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/core/machine.c')
0 files changed, 0 insertions, 0 deletions