diff options
| author | Igor Mammedov | 2020-10-06 17:00:02 +0200 |
|---|---|---|
| committer | Eduardo Habkost | 2020-10-06 17:09:41 +0200 |
| commit | 1b5e843ab68c4afa611da22f303a5b0daa979ad8 (patch) | |
| tree | 3fd216b072074a64b8273591d1aa5d643df8a8dd /hw/core/numa.c | |
| parent | kernel-doc: Remove $decl_type='type name' hack (diff) | |
| download | qemu-1b5e843ab68c4afa611da22f303a5b0daa979ad8.tar.gz qemu-1b5e843ab68c4afa611da22f303a5b0daa979ad8.tar.xz qemu-1b5e843ab68c4afa611da22f303a5b0daa979ad8.zip | |
numa: hmat: require parent cache description before the next level one
Spec[1] defines 0 - 3 level memory side cache, however QEMU
CLI allows to specify an intermediate cache level without
specifying previous level. Such option(s) silently ignored
when building HMAT table, which leads to incomplete cache
information.
Make sure that previous level exists and error out
if it hasn't been provided.
1) ACPI 6.2A 5.2.27.5 Memory Side Cache Information Structure
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1842877
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20201006150002.1601845-1-imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'hw/core/numa.c')
| -rw-r--r-- | hw/core/numa.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/hw/core/numa.c b/hw/core/numa.c index 7d5d413001..7c4dd4e68e 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -424,7 +424,13 @@ void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, } if ((node->level > 1) && - ms->numa_state->hmat_cache[node->node_id][node->level - 1] && + ms->numa_state->hmat_cache[node->node_id][node->level - 1] == NULL) { + error_setg(errp, "Cache level=%u shall be defined first", + node->level - 1); + return; + } + + if ((node->level > 1) && (node->size <= ms->numa_state->hmat_cache[node->node_id][node->level - 1]->size)) { error_setg(errp, "Invalid size=%" PRIu64 ", the size of level=%" PRIu8 |