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| author | Anup Patel | 2018-12-14 20:12:32 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2018-12-20 21:26:39 +0100 |
| commit | 71a150bc914ef154d1321cc3602a4e80a433fc52 (patch) | |
| tree | 443d2b097ee1500acbce6869ba0c0a44a06c6f19 /hw/core/qdev.c | |
| parent | sifive_uart: Implement interrupt pending register (diff) | |
| download | qemu-71a150bc914ef154d1321cc3602a4e80a433fc52.tar.gz qemu-71a150bc914ef154d1321cc3602a4e80a433fc52.tar.xz qemu-71a150bc914ef154d1321cc3602a4e80a433fc52.zip | |
target/riscv/pmp.c: Fix pmp_decode_napot()
Currently, start and end address of a PMP region are not decoded
correctly by pmp_decode_napot().
Let's say we have a 128KB PMP region with base address as 0x80000000.
Now, the PMPADDRx CSR value for this region will be 0x20003fff.
The current pmp_decode_napot() implementation will decode PMPADDRx
CSR as t1=14, base=0x100000000, and range=0x1ffff whereas it should
have decoded PMPADDRx CSR as t1=14, base=0x80000000, and range=0x1fff.
This patch fixes the base value decoding in pmp_decode_napot() when
PMPADDRx CSR is not -1 (i.e. 0xffffffffffffffff).
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/core/qdev.c')
0 files changed, 0 insertions, 0 deletions