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| author | Richard Henderson | 2022-09-29 19:51:21 +0200 |
|---|---|---|
| committer | Richard Henderson | 2022-10-04 21:13:12 +0200 |
| commit | 1d41a79b3c7573c941723455149cfadfe7c2ab37 (patch) | |
| tree | 6eec27ed1eb95a4841e286156fdf2e7f48e533cc /hw/core/sysbus-fdt.c | |
| parent | accel/tcg: Do not align tb->page_addr[0] (diff) | |
| download | qemu-1d41a79b3c7573c941723455149cfadfe7c2ab37.tar.gz qemu-1d41a79b3c7573c941723455149cfadfe7c2ab37.tar.xz qemu-1d41a79b3c7573c941723455149cfadfe7c2ab37.zip | |
accel/tcg: Inline tb_flush_jmp_cache
This function has two users, who use it incompatibly.
In tlb_flush_page_by_mmuidx_async_0, when flushing a
single page, we need to flush exactly two pages.
In tlb_flush_range_by_mmuidx_async_0, when flushing a
range of pages, we need to flush N+1 pages.
This avoids double-flushing of jmp cache pages in a range.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/core/sysbus-fdt.c')
0 files changed, 0 insertions, 0 deletions