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author | Peter Maydell | 2019-01-21 18:53:28 +0100 |
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committer | Peter Maydell | 2019-01-21 18:53:28 +0100 |
commit | 166609e6070fab3424510ac7292ecb585f8b80fb (patch) | |
tree | c3493a4931636b8fe884172fa58a07e7223d99b2 /hw/core | |
parent | hw/virtio/virtio-balloon: zero-initialize the virtio_balloon_config struct (diff) | |
parent | target/mips: Introduce 32 R5900 multimedia registers (diff) | |
download | qemu-166609e6070fab3424510ac7292ecb585f8b80fb.tar.gz qemu-166609e6070fab3424510ac7292ecb585f8b80fb.tar.xz qemu-166609e6070fab3424510ac7292ecb585f8b80fb.zip |
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-january-17-2019-v2' into staging
MIPS queue for January 17, 2019 - v2
# gpg: Signature made Fri 18 Jan 2019 15:55:35 GMT
# gpg: using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-january-17-2019-v2:
target/mips: Introduce 32 R5900 multimedia registers
target/mips: Rename 'rn' to 'register_name'
target/mips: Add CP0 register MemoryMapID
target/mips: Amend preprocessor constants for CP0 registers
target/mips: Update ITU to handle bus errors
target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
target/mips: Add field and R/W access to ITU control register ICR0
target/mips: Provide R/W access to SAARI and SAAR CP0 registers
target/mips: Add fields for SAARI and SAAR CP0 registers
target/mips: Use preprocessor constants for 32 major CP0 registers
target/mips: Add preprocessor constants for 32 major CP0 registers
target/mips: Move comment containing summary of CP0 registers
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/core')
0 files changed, 0 insertions, 0 deletions