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| author | Hongren (Zenithal) Zheng | 2022-05-18 14:46:58 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-05-24 02:38:50 +0200 |
| commit | 5160bacc0638088a7cb0180d2be3d8c2c8a21831 (patch) | |
| tree | f4ba73b24ec68d81f9fb05bbedca7b15d39352c2 /hw/core | |
| parent | hw/riscv: virt: Fix interrupt parent for dynamic platform devices (diff) | |
| download | qemu-5160bacc0638088a7cb0180d2be3d8c2c8a21831.tar.gz qemu-5160bacc0638088a7cb0180d2be3d8c2c8a21831.tar.xz qemu-5160bacc0638088a7cb0180d2be3d8c2c8a21831.zip | |
target/riscv: add zicsr/zifencei to isa_string
Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.
Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/core')
0 files changed, 0 insertions, 0 deletions