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authorRichard Henderson2022-06-11 03:15:34 +0200
committerRichard Henderson2022-06-11 03:15:34 +0200
commit30796f556790631c86c733ab06756981be0e1def (patch)
tree3a422366aa9856d1ed62632335610904950b7256 /hw/cxl/cxl-host.c
parentMerge tag 'pull-target-arm-20220610' of https://git.linaro.org/people/pmaydel... (diff)
parenthw/vhost-user-scsi|blk: set `supports_config` flag correctly (diff)
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Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: fixes,cleanups,features more CXL patches VIOT Igor's huge AML rework fixes, cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmKj4YcPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpkNcIAKTsMfUVueTjelC2RwIdegQkypycKhCweKzc # QxddaEr0w+N2164byT3IUy9h53hV3qAAmMuGE4d8B2r5rykf+SwDfIeNmHNqntnA # oLraXIxSSAf4/1cTsRCVL/BXo2E9P+WHI3huw37HClmPLdyMjQa1AtpTpKnIsbmO # sBZf7t5yHDJ2WGZwBQ1IbAxvsdGo1fa1TCt1jZ9g1dmnQSTteQG8DHkGoRnkwTi7 # 510jb0e8uQEgKytCdLTHqESHlfgjvoI73OFOAR2dzTKy6KelFmdLYSo2FtsIdtT5 # 1fZNaDjtl6zQ4b2iLBgPpHtikKch9BzzhDMbCsq7FpvasZ8u2FE= # =LXG0 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 10 Jun 2022 05:27:51 PM PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (53 commits) hw/vhost-user-scsi|blk: set `supports_config` flag correctly hw/virtio/vhost-user: don't use uninitialized variable tests/acpi: virt: update golden masters for VIOT hw/acpi/viot: sort VIOT ACPI table entries by PCI host bridge min_bus tests/acpi: virt: allow VIOT acpi table changes hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table hw/acpi/viot: move the individual PCI host bridge entry generation to a new function hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges() hw/cxl: Fix missing write mask for HDM decoder target list registers pci: fix overflow in snprintf string formatting hw/machine: Drop cxl_supported flag as no longer useful hw/cxl: Move the CXLState from MachineState to machine type specific state. tests/acpi: Update q35/CEDT.cxl for new memory addresses. pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup. tests/acpi: Allow modification of q35 CXL CEDT table. hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c hw/acpi/cxl: Pass in the CXLState directly rather than MachineState hw/cxl: Make the CXL fixed memory window setup a machine parameter. x86: acpi-build: do not include hw/isa/isa.h directly tests: acpi: update expected DSDT.tis.tpm2/DSDT.tis.tpm12 blobs ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/cxl/cxl-host.c')
-rw-r--r--hw/cxl/cxl-host.c100
1 files changed, 90 insertions, 10 deletions
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index 469b3c4ced..efa14908d8 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -15,14 +15,16 @@
#include "qapi/qapi-visit-machine.h"
#include "hw/cxl/cxl.h"
+#include "hw/cxl/cxl_host.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_host.h"
#include "hw/pci/pcie_port.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
-void cxl_fixed_memory_window_config(MachineState *ms,
- CXLFixedMemoryWindowOptions *object,
- Error **errp)
+static void cxl_fixed_memory_window_config(CXLState *cxl_state,
+ CXLFixedMemoryWindowOptions *object,
+ Error **errp)
{
CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
strList *target;
@@ -62,20 +64,17 @@ void cxl_fixed_memory_window_config(MachineState *ms,
fw->enc_int_gran = 0;
}
- ms->cxl_devices_state->fixed_windows =
- g_list_append(ms->cxl_devices_state->fixed_windows, fw);
+ cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows, fw);
return;
}
-void cxl_fixed_memory_window_link_targets(Error **errp)
+void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
-
- if (ms->cxl_devices_state && ms->cxl_devices_state->fixed_windows) {
+ if (cxl_state && cxl_state->fixed_windows) {
GList *it;
- for (it = ms->cxl_devices_state->fixed_windows; it; it = it->next) {
+ for (it = cxl_state->fixed_windows; it; it = it->next) {
CXLFixedWindow *fw = it->data;
int i;
@@ -220,3 +219,84 @@ const MemoryRegionOps cfmws_ops = {
.unaligned = true,
},
};
+
+static void machine_get_cxl(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLState *cxl_state = opaque;
+ bool value = cxl_state->is_enabled;
+
+ visit_type_bool(v, name, &value, errp);
+}
+
+static void machine_set_cxl(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLState *cxl_state = opaque;
+ bool value;
+
+ if (!visit_type_bool(v, name, &value, errp)) {
+ return;
+ }
+ cxl_state->is_enabled = value;
+}
+
+static void machine_get_cfmw(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLFixedMemoryWindowOptionsList **list = opaque;
+
+ visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp);
+}
+
+static void machine_set_cfmw(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLState *state = opaque;
+ CXLFixedMemoryWindowOptionsList *cfmw_list = NULL;
+ CXLFixedMemoryWindowOptionsList *it;
+
+ visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp);
+ if (!cfmw_list) {
+ return;
+ }
+
+ for (it = cfmw_list; it; it = it->next) {
+ cxl_fixed_memory_window_config(state, it->value, errp);
+ }
+ state->cfmw_list = cfmw_list;
+}
+
+void cxl_machine_init(Object *obj, CXLState *state)
+{
+ object_property_add(obj, "cxl", "bool", machine_get_cxl,
+ machine_set_cxl, NULL, state);
+ object_property_set_description(obj, "cxl",
+ "Set on/off to enable/disable "
+ "CXL instantiation");
+
+ object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
+ machine_get_cfmw, machine_set_cfmw,
+ NULL, state);
+ object_property_set_description(obj, "cxl-fmw",
+ "CXL Fixed Memory Windows (array)");
+}
+
+void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)
+{
+ /* Walk the pci busses looking for pxb busses to hook up */
+ if (bus) {
+ QLIST_FOREACH(bus, &bus->child, sibling) {
+ if (!pci_bus_is_root(bus)) {
+ continue;
+ }
+ if (pci_bus_is_cxl(bus)) {
+ if (!state->is_enabled) {
+ error_setg(errp, "CXL host bridges present, but cxl=off");
+ return;
+ }
+ pxb_cxl_hook_up_registers(state, bus, errp);
+ }
+ }
+ }
+}