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authorBALATON Zoltan2017-04-21 17:18:09 +0200
committerPeter Maydell2017-04-24 13:32:12 +0200
commite2ee84760e8af52f085b95f562d850b8eb739072 (patch)
treedcbbb9f8d290ce09d66263a84678679b20d688bd /hw/display/sm501.c
parentsm501: Fixed code style and a few typos in comments (diff)
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sm501: Use defined constants instead of literal values where available
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Message-id: 31205c2df623e7b133ef942ff4f5e95fff800a14.1492787889.git.balaton@eik.bme.hu Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/display/sm501.c')
-rw-r--r--hw/display/sm501.c29
1 files changed, 19 insertions, 10 deletions
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 4f40dee9c6..6b72964e1e 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -23,6 +23,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
@@ -446,12 +447,12 @@
/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
static const uint32_t sm501_mem_local_size[] = {
- [0] = 4 * 1024 * 1024,
- [1] = 8 * 1024 * 1024,
- [2] = 16 * 1024 * 1024,
- [3] = 32 * 1024 * 1024,
- [4] = 64 * 1024 * 1024,
- [5] = 2 * 1024 * 1024,
+ [0] = 4 * M_BYTE,
+ [1] = 8 * M_BYTE,
+ [2] = 16 * M_BYTE,
+ [3] = 32 * M_BYTE,
+ [4] = 64 * M_BYTE,
+ [5] = 2 * M_BYTE,
};
#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
@@ -555,7 +556,7 @@ static uint32_t get_local_mem_size_index(uint32_t size)
static inline int is_hwc_enabled(SM501State *state, int crt)
{
uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
- return addr & 0x80000000;
+ return addr & SM501_HWC_EN;
}
/**
@@ -1411,9 +1412,17 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
s->local_mem_size_index);
- s->system_control = 0x00100000;
- s->misc_control = 0x00001000; /* assumes SH, active=low */
- s->dc_panel_control = 0x00010000;
+ s->system_control = 0x00100000; /* 2D engine FIFO empty */
+ /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
+ * to be determined at reset by GPIO lines which set config bits.
+ * We hardwire them:
+ * SH = 0 : Hitachi Ready Polarity == Active Low
+ * CDR = 0 : do not reset clock divider
+ * TEST = 0 : Normal mode (not testing the silicon)
+ * BUS = 0 : Hitachi SH3/SH4
+ */
+ s->misc_control = SM501_MISC_DAC_POWER;
+ s->dc_panel_control = 0x00010000; /* FIFO level 3 */
s->dc_crt_control = 0x00010000;
/* allocate local memory */