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| author | Konrad Rzeszutek Wilk | 2018-05-21 23:54:24 +0200 |
|---|---|---|
| committer | Eduardo Habkost | 2018-05-21 23:59:08 +0200 |
| commit | cfeea0c021db6234c154dbc723730e81553924ff (patch) | |
| tree | d72e36a2202ff276ca218b6cc07f3fd30879b0d3 /hw/display | |
| parent | i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639) (diff) | |
| download | qemu-cfeea0c021db6234c154dbc723730e81553924ff.tar.gz qemu-cfeea0c021db6234c154dbc723730e81553924ff.tar.xz qemu-cfeea0c021db6234c154dbc723730e81553924ff.zip | |
i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)
"Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD). To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a
hypervisor can virtualize the existence of this definition and provide an
architectural method for using SSBD to a guest.
Add the new CPUID feature, the new MSR and update the existing SSBD
support to use this MSR when present." (from x86/speculation: Add virtualized
speculative store bypass disable support in Linux).
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20180521215424.13520-4-berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'hw/display')
0 files changed, 0 insertions, 0 deletions