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| author | Xuzhou Cheng | 2021-03-03 14:52:50 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-08 18:20:04 +0100 |
| commit | 35593573b25f8774ce16be8a7d703b7740964e81 (patch) | |
| tree | 59f3e06ff448de3d1cc14e5d4b51de20d9ff24ae /hw/dma/meson.build | |
| parent | target/arm: Restrict v7A TCG cpus to TCG accel (diff) | |
| download | qemu-35593573b25f8774ce16be8a7d703b7740964e81.tar.gz qemu-35593573b25f8774ce16be8a7d703b7740964e81.tar.xz qemu-35593573b25f8774ce16be8a7d703b7740964e81.zip | |
hw/dma: Implement a Xilinx CSU DMA model
ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
is unimplemented. When QSPI is programmed to use DMA mode, QEMU will
crash. This is observed when testing VxWorks 7.
This adds a Xilinx CSU DMA model and the implementation is based on
https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c.
The DST part of the model is verified along with ZynqMP GQSPI model.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-2-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/dma/meson.build')
| -rw-r--r-- | hw/dma/meson.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/dma/meson.build b/hw/dma/meson.build index 47b4a7cb47..5c78a4e05f 100644 --- a/hw/dma/meson.build +++ b/hw/dma/meson.build @@ -14,3 +14,4 @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_CSU_DMA', if_true: files('xlnx_csu_dma.c')) |