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| author | Bin Meng | 2020-09-01 03:39:04 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:18 +0200 |
| commit | 97ba42230b28636e02ab0af77738bb247e051dd4 (patch) | |
| tree | 3729a707093e871611f7c005a9c000233dd0bf9a /hw/dma/meson.build | |
| parent | hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card (diff) | |
| download | qemu-97ba42230b28636e02ab0af77738bb247e051dd4.tar.gz qemu-97ba42230b28636e02ab0af77738bb247e051dd4.tar.xz qemu-97ba42230b28636e02ab0af77738bb247e051dd4.zip | |
hw/dma: Add SiFive platform DMA controller emulation
Microchip PolarFire SoC integrates a DMA engine that supports:
* Independent concurrent DMA transfers using 4 DMA channels
* Generation of interrupts on various conditions during execution
which is actually an IP reused from the SiFive FU540 chip.
This creates a model to support both polling and interrupt modes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/dma/meson.build')
| -rw-r--r-- | hw/dma/meson.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/dma/meson.build b/hw/dma/meson.build index ff5bb3748f..b991d7698c 100644 --- a/hw/dma/meson.build +++ b/hw/dma/meson.build @@ -13,3 +13,4 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c')) |