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| author | Bin Meng | 2021-09-27 09:21:23 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-10-07 00:41:33 +0200 |
| commit | b7af62ae2ca4a5f36a36d98e37d59e96fb3f8ef5 (patch) | |
| tree | 047c1e4cf7ff7c4942f13d758a32902f0ef380f8 /hw/dma | |
| parent | hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART (diff) | |
| download | qemu-b7af62ae2ca4a5f36a36d98e37d59e96fb3f8ef5.tar.gz qemu-b7af62ae2ca4a5f36a36d98e37d59e96fb3f8ef5.tar.xz qemu-b7af62ae2ca4a5f36a36d98e37d59e96fb3f8ef5.zip | |
hw/dma: sifive_pdma: Fix Control.claim bit detection
At present the codes detect whether the DMA channel is claimed by:
claimed = !!s->chan[ch].control & CONTROL_CLAIM;
As ! has higher precedence over & (bitwise and), this is essentially
claimed = (!!s->chan[ch].control) & CONTROL_CLAIM;
which is wrong, as any non-zero bit set in the control register will
produce a result of a claimed channel.
Fixes: de7c7988d25d ("hw/dma: sifive_pdma: reset Next* registers when Control.claim is set")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210927072124.1564129-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/dma')
| -rw-r--r-- | hw/dma/sifive_pdma.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index b4fd40573a..b8ec7621f3 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -243,7 +243,7 @@ static void sifive_pdma_write(void *opaque, hwaddr offset, offset &= 0xfff; switch (offset) { case DMA_CONTROL: - claimed = !!s->chan[ch].control & CONTROL_CLAIM; + claimed = !!(s->chan[ch].control & CONTROL_CLAIM); if (!claimed && (value & CONTROL_CLAIM)) { /* reset Next* registers */ |