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author | j_mayer | 2007-10-29 00:42:18 +0100 |
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committer | j_mayer | 2007-10-29 00:42:18 +0100 |
commit | 3cbee15b9a6be17645e908bf7706d582c3e17156 (patch) | |
tree | b89a5f1cfea3fdb8e95325108afc229a3ec3fa9e /hw/grackle_pci.c | |
parent | Give an opaque to the m48t59 direct access routines to make it easier (diff) | |
download | qemu-3cbee15b9a6be17645e908bf7706d582c3e17156.tar.gz qemu-3cbee15b9a6be17645e908bf7706d582c3e17156.tar.xz qemu-3cbee15b9a6be17645e908bf7706d582c3e17156.zip |
* sort the PowerPC target object files
* make PowerPC NVRAM accessors generic to be able to use a MacIO NVRAM
instead of the M48T59 one
* split PowerMac targets code:
- move all PowerMac related definitions and prototypes into hw/ppc_mac.h
- add hw/mac_dbdma.c, hw/mac_nvram.c and macio.c
which implements shared PowerMac devices
- define the g3bw machine in a new hw/ppc_oldworld.c file
* Fix the g3bw target:
- fix the Grackle host PCI device
- connect the Heathrow PIC to the PowerPC 6xx bus pins
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3475 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/grackle_pci.c')
-rw-r--r-- | hw/grackle_pci.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c index fb46051664..85c434c8e8 100644 --- a/hw/grackle_pci.c +++ b/hw/grackle_pci.c @@ -1,7 +1,8 @@ /* - * QEMU Grackle (heathrow PPC) PCI host + * QEMU Grackle PCI host (heathrow OldWorld PowerMac) * - * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2006-2007 Fabrice Bellard + * Copyright (c) 2007 Jocelyn Mayer * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,6 +24,7 @@ */ #include "vl.h" +#include "ppc_mac.h" typedef target_phys_addr_t pci_addr_t; #include "pci_host.h" @@ -82,7 +84,7 @@ static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level) { - qemu_set_irq(pic[irq_num + 8], level); + qemu_set_irq(pic[irq_num + 0x15], level); } PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) @@ -93,7 +95,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) s = qemu_mallocz(sizeof(GrackleState)); s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq, - pic, 0, 0); + pic, 0, 4); pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read, pci_grackle_config_write, s); |