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| author | Blue Swirl | 2011-09-17 22:30:50 +0200 |
|---|---|---|
| committer | Blue Swirl | 2011-09-27 21:16:46 +0200 |
| commit | 46f3069cba94aab44b3b4f87bc270759b4a700fa (patch) | |
| tree | 6f9073a78aaa91f42a559116ec63205d57124866 /hw/grackle_pci.c | |
| parent | Merge remote-tracking branch 'qemu-kvm-tmp/memory/urgent' into staging (diff) | |
| download | qemu-46f3069cba94aab44b3b4f87bc270759b4a700fa.tar.gz qemu-46f3069cba94aab44b3b4f87bc270759b4a700fa.tar.xz qemu-46f3069cba94aab44b3b4f87bc270759b4a700fa.zip | |
PPC: use memory API to construct the PCI hole
Avoid vga.chain4 mapping by constructing a PCI hole for upper
2G of the PCI space.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/grackle_pci.c')
| -rw-r--r-- | hw/grackle_pci.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c index 9d3ff7d555..94a608ef6d 100644 --- a/hw/grackle_pci.c +++ b/hw/grackle_pci.c @@ -41,6 +41,8 @@ typedef struct GrackleState { SysBusDevice busdev; PCIHostState host_state; + MemoryRegion pci_mmio; + MemoryRegion pci_hole; } GrackleState; /* Don't know if this matches real hardware, but it agrees with OHW. */ @@ -73,11 +75,18 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic, qdev_init_nofail(dev); s = sysbus_from_qdev(dev); d = FROM_SYSBUS(GrackleState, s); + + memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL); + memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio, + 0x80000000ULL, 0x7e000000ULL); + memory_region_add_subregion(address_space_mem, 0x80000000ULL, + &d->pci_hole); + d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", pci_grackle_set_irq, pci_grackle_map_irq, pic, - address_space_mem, + &d->pci_mmio, address_space_io, 0, 4); |