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| author | Aaron Lindsay | 2018-10-10 22:37:23 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-10-16 18:14:55 +0200 |
| commit | 599b71e277ac7e92807191b20b7163a28c5450ad (patch) | |
| tree | 629070c14884077d7175290a458da5ab81cebbfc /hw/hyperv/hyperv.c | |
| parent | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO (diff) | |
| download | qemu-599b71e277ac7e92807191b20b7163a28c5450ad.tar.gz qemu-599b71e277ac7e92807191b20b7163a28c5450ad.tar.xz qemu-599b71e277ac7e92807191b20b7163a28c5450ad.zip | |
target/arm: Mask PMOVSR writes based on supported counters
This is an amendment to my earlier patch:
commit 7ece99b17e832065236c07a158dfac62619ef99b
Author: Aaron Lindsay <alindsay@codeaurora.org>
Date: Thu Apr 26 11:04:39 2018 +0100
target/arm: Mask PMU register writes based on PMCR_EL0.N
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181010203735.27918-3-aclindsa@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/hyperv/hyperv.c')
0 files changed, 0 insertions, 0 deletions