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| author | Peter Maydell | 2017-01-19 19:34:13 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-01-19 19:34:13 +0100 |
| commit | 0f6bcf68a99efdc531b209551f2b760b0bdcc554 (patch) | |
| tree | 85fa52c14378c6c75548b3e8939180a016a69a18 /hw/i2c/aspeed_i2c.c | |
| parent | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170117' into staging (diff) | |
| parent | target-sparc: fix up niagara machine (diff) | |
| download | qemu-0f6bcf68a99efdc531b209551f2b760b0bdcc554.tar.gz qemu-0f6bcf68a99efdc531b209551f2b760b0bdcc554.tar.xz qemu-0f6bcf68a99efdc531b209551f2b760b0bdcc554.zip | |
Merge remote-tracking branch 'remotes/artyom/tags/pull-sun4v-20170118' into staging
add OpenSPARC T1 emulation
# gpg: Signature made Wed 18 Jan 2017 22:25:47 GMT
# gpg: using RSA key 0x3360C3F7411A125F
# gpg: Good signature from "Artyom Tarasenko <atar4qemu@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 2AD8 6149 17F4 B2D7 05C0 BB12 3360 C3F7 411A 125F
* remotes/artyom/tags/pull-sun4v-20170118: (30 commits)
target-sparc: fix up niagara machine
target-sparc: move common cpu initialisation routines to sparc64.c
target-sparc: implement sun4v RTC
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs
target-sparc: store the UA2005 entries in sun4u format
target-sparc: implement UA2005 ASI_MMU (0x21)
target-sparc: add more registers to dump_mmu
target-sparc: implement auto-demapping for UA2005 CPUs
target-sparc: allow 256M sized pages
target-sparc: simplify ultrasparc_tsb_pointer
target-sparc: implement UA2005 TSB Pointers
target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs
target-sparc: replace the last tlb entry when no free entries left
target-sparc: ignore writes to UA2005 CPU mondo queue register
target-sparc: allow priveleged ASIs in hyperprivileged mode
target-sparc: use direct address translation in hyperprivileged mode
target-sparc: fix immediate UA2005 traps
target-sparc: implement UA2005 rdhpstate and wrhpstate instructions
target-sparc: implement UA2005 GL register
target-sparc: implement UA2005 hypervisor traps
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/i2c/aspeed_i2c.c')
0 files changed, 0 insertions, 0 deletions