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authorStefan Hajnoczi2022-10-26 16:04:05 +0200
committerStefan Hajnoczi2022-10-26 16:04:05 +0200
commit7c02614ec97f02aef888c1ecdcfbf396035d4871 (patch)
tree8223f9fe499515981d0ac081d3e328b41093d962 /hw/i2c/aspeed_i2c.c
parentMerge tag 'trivial-branch-for-7.2-pull-request' of https://gitlab.com/laurent... (diff)
parentarm/aspeed: Replace mx25l25635e chip model (diff)
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Merge tag 'pull-aspeed-20221025' of https://github.com/legoater/qemu into staging
aspeed queue : * Performance improvement with Object class caching * Serial Flash Discovery Parameters support for m25p80 device * Various small adjustments on intructions and models # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmNX/WEACgkQUaNDx8/7 # 7KFhERAAhrcLcv15ny8RwatHPjzU00ZPQ0PcxGj1VDT66pCVh6M+rIeRPB2scOey # Pu8jUvIYJ8w7ozjAP6YTQ1MP/WufniVi91Bx+vs/okSiWZa4dP0/G7NQWoc1at0s # NBlkg57l1GMEeQb5x8vC1DizTQ1Z8Q8J/Ur3uXukXCmYVJAwHYpl/Foob1IPFgh8 # UcJ55LyuRq99lS8ib6HvRftAsC3DOcA/sl3b/TYR2+iKyi1VS2aZoQzxVCavSBcz # PoTonT9O4OvIQthAgXRwpylW/aMYU3I7FeyOMKlCNLbmJ8LpVbX2v0KN3WBvWBv4 # OWP0DiqPUuoWFHLUGKbiVOgWQrTQXZyoD70SD/ObE1oMTLmeBoD1oFizQDvokHAR # g2+gMdWnuWcbyaofY7YwuI6qz22gbrgh8JqX6sEWRDnY7HgCUvPhCsmci+bdN5cf # dGcE8YKi7aD5gzoU9LRziPlhbwaEsgYLpYS7aGfNcmypgeq6lmNG7xKyw911zCTY # uqDZWOUJy0tUIUTxoz3o1/KtsTFugjuZ+9W1SxELptJR37iwlP1vumf6bduwcx/3 # ba8tzNoXecXO5Icmq5P3lMNVM/abpkDDKS66HA87mABLEd/eCD0ojR9Kfxo0mD74 # kmQK3MFfJPkTu0ddu1cWhCIgTO7EuLuZL7gzj1oxoeXiU3YcVh8= # =u7pS # -----END PGP SIGNATURE----- # gpg: Signature made Tue 25 Oct 2022 11:14:41 EDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20221025' of https://github.com/legoater/qemu: arm/aspeed: Replace mx25l25635e chip model m25p80: Add the w25q01jvq SFPD table m25p80: Add the w25q512jv SFPD table m25p80: Add the w25q256 SFPD table m25p80: Add the mx66l1g45g SFDP table m25p80: Add the mx25l25635f SFPD table m25p80: Add the mx25l25635e SFPD table m25p80: Add erase size for mx25l25635e m25p80: Add the n25q256a SFDP table m25p80: Add basic support for the SFDP command hw/arm/aspeed: increase Bletchley memory size ast2600: Drop NEON from the CPU features aspeed/smc: Cache AspeedSMCClass ssi: cache SSIPeripheralClass to avoid GET_CLASS() tests/avocado/machine_aspeed.py: Fix typos on buildroot hw/i2c/aspeed: Fix old reg slave receive Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'hw/i2c/aspeed_i2c.c')
-rw-r--r--hw/i2c/aspeed_i2c.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 42c6d69b82..c166fd20fa 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1131,7 +1131,9 @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent);
uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
- uint32_t value;
+ uint32_t reg_dev_addr = aspeed_i2c_bus_dev_addr_offset(bus);
+ uint32_t dev_addr = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_dev_addr,
+ SLAVE_DEV_ADDR1);
if (aspeed_i2c_is_new_mode(bus->controller)) {
return aspeed_i2c_bus_new_slave_event(bus, event);
@@ -1139,8 +1141,8 @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
switch (event) {
case I2C_START_SEND_ASYNC:
- value = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_byte_buf, TX_BUF);
- SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, value << 1);
+ /* Bit[0] == 0 indicates "send". */
+ SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, dev_addr << 1);
ARRAY_FIELD_DP32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 1);
SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1);