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authorAlistair Francis2021-04-24 05:34:12 +0200
committerAlistair Francis2021-05-11 12:02:07 +0200
commitdaf866b606bdb94bb7c7ac6621353d30958521d8 (patch)
tree97fd6f2f4a30ecec2585096bf5bc4ba403505cef /hw/i2c/exynos4210_i2c.c
parenttarget/riscv: Remove an unused CASE_OP_32_64 macro (diff)
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target/riscv: Consolidate RV32/64 32-bit instructions
This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/i2c/exynos4210_i2c.c')
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