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authorPeter Maydell2019-11-25 16:47:44 +0100
committerPeter Maydell2019-11-25 16:47:44 +0100
commit65e05c82bdc6d348155e301c9d87dba7a08a5701 (patch)
tree99e413c0c6bfbffbec5ac7392c3652c625f3f0f0 /hw/i386/intel_iommu.c
parentMerge remote-tracking branch 'remotes/armbru/tags/pull-misc-2019-11-25' into ... (diff)
parentintel_iommu: TM field should not be in reserved bits (diff)
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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
virtio, pc: fixes More small bugfixes. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 25 Nov 2019 08:43:07 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: intel_iommu: TM field should not be in reserved bits intel_iommu: refine SL-PEs reserved fields checking virtio-input: fix memory leak on unrealize Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/i386/intel_iommu.c')
-rw-r--r--hw/i386/intel_iommu.c40
1 files changed, 23 insertions, 17 deletions
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 14e4e6ad62..43c94b993b 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -910,19 +910,23 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
/*
* Rsvd field masks for spte:
- * Index [1] to [4] 4k pages
- * Index [5] to [8] large pages
+ * vtd_spte_rsvd 4k pages
+ * vtd_spte_rsvd_large large pages
*/
-static uint64_t vtd_paging_entry_rsvd_field[9];
+static uint64_t vtd_spte_rsvd[5];
+static uint64_t vtd_spte_rsvd_large[5];
static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
{
- if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
- /* Maybe large page */
- return slpte & vtd_paging_entry_rsvd_field[level + 4];
- } else {
- return slpte & vtd_paging_entry_rsvd_field[level];
+ uint64_t rsvd_mask = vtd_spte_rsvd[level];
+
+ if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) &&
+ (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) {
+ /* large page */
+ rsvd_mask = vtd_spte_rsvd_large[level];
}
+
+ return slpte & rsvd_mask;
}
/* Find the VTD address space associated with a given bus number */
@@ -3549,15 +3553,17 @@ static void vtd_init(IntelIOMMUState *s)
/*
* Rsvd field masks for spte
*/
- vtd_paging_entry_rsvd_field[0] = ~0ULL;
- vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[0] = ~0ULL;
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
+
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
if (x86_iommu_ir_supported(x86_iommu)) {
s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;