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authorLiu, Yi L2019-03-05 03:34:54 +0100
committerMichael S. Tsirkin2019-03-13 03:31:21 +0100
commitc0c1d351849bc249304e0c505e1597e570d1e777 (patch)
tree8f0b6665a0985b60b1f4edac39755d12189499c1 /hw/i386/intel_iommu_internal.h
parentintel_iommu: scalable mode emulation (diff)
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intel_iommu: add 256 bits qi_desc support
Per Intel(R) VT-d 3.0, the qi_desc is 256 bits in Scalable Mode. This patch adds emulation of 256bits qi_desc. Signed-off-by: Liu, Yi L <yi.l.liu@intel.com> [Yi Sun is co-developer to rebase and refine the patch.] Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <1551753295-30167-3-git-send-email-yi.y.sun@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386/intel_iommu_internal.h')
-rw-r--r--hw/i386/intel_iommu_internal.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index fe72bc38f0..016fa4c7c5 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -190,6 +190,7 @@
#define VTD_ECAP_EIM (1ULL << 4)
#define VTD_ECAP_PT (1ULL << 6)
#define VTD_ECAP_MHMV (15ULL << 20)
+#define VTD_ECAP_SMTS (1ULL << 43)
/* CAP_REG */
/* (offset >> 4) << 24 */
@@ -218,11 +219,14 @@
#define VTD_CAP_SAGAW_48bit (0x4ULL << VTD_CAP_SAGAW_SHIFT)
/* IQT_REG */
-#define VTD_IQT_QT(val) (((val) >> 4) & 0x7fffULL)
+#define VTD_IQT_QT(dw_bit, val) (dw_bit ? (((val) >> 5) & 0x3fffULL) : \
+ (((val) >> 4) & 0x7fffULL))
+#define VTD_IQT_QT_256_RSV_BIT 0x10
/* IQA_REG */
#define VTD_IQA_IQA_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL)
#define VTD_IQA_QS 0x7ULL
+#define VTD_IQA_DW_MASK 0x800
/* IQH_REG */
#define VTD_IQH_QH_SHIFT 4
@@ -324,6 +328,9 @@ union VTDInvDesc {
uint64_t lo;
uint64_t hi;
};
+ struct {
+ uint64_t val[4];
+ };
union {
VTDInvDescIEC iec;
};