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| author | David Woodhouse | 2020-10-05 16:18:19 +0200 |
|---|---|---|
| committer | Paolo Bonzini | 2020-12-10 18:15:00 +0100 |
| commit | c1bb5418e32ec70c72af332354b5963eab7a5579 (patch) | |
| tree | 5450a1ff1d4fcf48602f1c21e49852c4f9bb7e73 /hw/i386/multiboot.h | |
| parent | target/i386: fix operand order for PDEP and PEXT (diff) | |
| download | qemu-c1bb5418e32ec70c72af332354b5963eab7a5579.tar.gz qemu-c1bb5418e32ec70c72af332354b5963eab7a5579.tar.xz qemu-c1bb5418e32ec70c72af332354b5963eab7a5579.zip | |
target/i386: Support up to 32768 CPUs without IRQ remapping
The IOAPIC has an 'Extended Destination ID' field in its RTE, which maps
to bits 11-4 of the MSI address. Since those address bits fall within a
given 4KiB page they were historically non-trivial to use on real hardware.
The Intel IOMMU uses the lowest bit to indicate a remappable format MSI,
and then the remaining 7 bits are part of the index.
Where the remappable format bit isn't set, we can actually use the other
seven to allow external (IOAPIC and MSI) interrupts to reach up to 32768
CPUs instead of just the 255 permitted on bare metal.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Message-Id: <78097f9218300e63e751e077a0a5ca029b56ba46.camel@infradead.org>
[Fix UBSAN warning. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Diffstat (limited to 'hw/i386/multiboot.h')
0 files changed, 0 insertions, 0 deletions