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| author | Jonathan Cameron | 2022-04-29 16:40:38 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin | 2022-05-13 12:13:36 +0200 |
| commit | abb3009baf90e5984ff1c230af0bc92a45e64864 (patch) | |
| tree | 64dc0af747f36a82600d2ccc18deb2410f804e48 /hw/i386/pc.c | |
| parent | hw/pci/cxl: Create a CXL bus type (diff) | |
| download | qemu-abb3009baf90e5984ff1c230af0bc92a45e64864.tar.gz qemu-abb3009baf90e5984ff1c230af0bc92a45e64864.tar.xz qemu-abb3009baf90e5984ff1c230af0bc92a45e64864.zip | |
cxl: Machine level control on whether CXL support is enabled
There are going to be some potential overheads to CXL enablement,
for example the host bridge region reserved in memory maps.
Add a machine level control so that CXL is disabled by default.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-14-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386/pc.c')
| -rw-r--r-- | hw/i386/pc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 305d2c0820..45e2d6092f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1761,6 +1761,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; mc->nvdimm_supported = true; mc->smp_props.dies_supported = true; + mc->cxl_supported = true; mc->default_ram_id = "pc.ram"; object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", |