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| author | Joao Martins | 2022-07-19 19:00:12 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin | 2022-07-26 16:40:58 +0200 |
| commit | 1caab5cf86bdf02fa71079c4ca4a3c0748f39eb5 (patch) | |
| tree | 12c1ede82ceca535f04952db9c984b947e29b571 /hw/i386/sgx.c | |
| parent | i386/pc: factor out device_memory base/size to helper (diff) | |
| download | qemu-1caab5cf86bdf02fa71079c4ca4a3c0748f39eb5.tar.gz qemu-1caab5cf86bdf02fa71079c4ca4a3c0748f39eb5.tar.xz qemu-1caab5cf86bdf02fa71079c4ca4a3c0748f39eb5.zip | |
i386/pc: bounds check phys-bits against max used GPA
Calculate max *used* GPA against the CPU maximum possible address
and error out if the former surprasses the latter. This ensures
max used GPA is reacheable by configured phys-bits. Default phys-bits
on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough for the CPU to
address 1Tb (0xff ffff ffff) or 1010G (0xfc ffff ffff) in AMD hosts
with IOMMU.
This is preparation for AMD guests with >1010G, where it will want relocate
ram-above-4g to be after 1Tb instead of 4G.
Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20220719170014.27028-10-joao.m.martins@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386/sgx.c')
0 files changed, 0 insertions, 0 deletions