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| author | Pawan Gupta | 2019-11-19 08:23:27 +0100 |
|---|---|---|
| committer | Paolo Bonzini | 2019-11-19 10:01:32 +0100 |
| commit | 7fac38635e1cc5ebae34eb6530da1009bd5808e4 (patch) | |
| tree | 7eaede164c578b61da2b928b16a4089dfc1fe851 /hw/i386 | |
| parent | target/i386: add PSCHANGE_NO bit for the ARCH_CAPABILITIES MSR (diff) | |
| download | qemu-7fac38635e1cc5ebae34eb6530da1009bd5808e4.tar.gz qemu-7fac38635e1cc5ebae34eb6530da1009bd5808e4.tar.xz qemu-7fac38635e1cc5ebae34eb6530da1009bd5808e4.zip | |
target/i386: Export TAA_NO bit to guests
TSX Async Abort (TAA) is a side channel attack on internal buffers in
some Intel processors similar to Microachitectural Data Sampling (MDS).
Some future Intel processors will use the ARCH_CAP_TAA_NO bit in the
IA32_ARCH_CAPABILITIES MSR to report that they are not vulnerable to
TAA. Make this bit available to guests.
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/i386')
0 files changed, 0 insertions, 0 deletions