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authorPeter Maydell2020-10-01 16:28:55 +0200
committerPeter Maydell2020-10-01 16:28:55 +0200
commitb23317eec4715aa62de9a6e5490a01122c8eef0e (patch)
tree4c46752e3d1092ab006305b3ca8f845ea348a342 /hw/i386
parentMerge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ... (diff)
parenttests/acpi: update expected data files (diff)
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Merge remote-tracking branch 'remotes/kraxel/tags/microvm-20200930-pull-request' into staging
microvm: add pcie support. # gpg: Signature made Wed 30 Sep 2020 18:48:41 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/microvm-20200930-pull-request: tests/acpi: update expected data files acpi/gpex: no reason to use a method for _CRS tests/acpi: add microvm pcie test tests/acpi: factor out common microvm test setup tests/acpi: add empty tests/data/acpi/microvm/DSDT.pcie file tests/acpi: allow updates for expected data files microvm/pcie: add 64bit mmio window microvm: add pcie support microvm: add irq table arm: use acpi_dsdt_add_gpex acpi: add acpi_dsdt_add_gpex move MemMapEntry Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/i386')
-rw-r--r--hw/i386/Kconfig1
-rw-r--r--hw/i386/acpi-microvm.c12
-rw-r--r--hw/i386/microvm.c93
3 files changed, 106 insertions, 0 deletions
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index d0bd8b537d..32aa15533b 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -104,6 +104,7 @@ config MICROVM
select MC146818RTC
select VIRTIO_MMIO
select ACPI_HW_REDUCED
+ select PCI_EXPRESS_GENERIC_BRIDGE
config X86_IOMMU
bool
diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c
index df39c5d3bd..f16f231195 100644
--- a/hw/i386/acpi-microvm.c
+++ b/hw/i386/acpi-microvm.c
@@ -33,6 +33,8 @@
#include "hw/boards.h"
#include "hw/i386/fw_cfg.h"
#include "hw/i386/microvm.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pcie_host.h"
#include "hw/virtio/virtio-mmio.h"
#include "acpi-common.h"
@@ -87,6 +89,15 @@ static void acpi_dsdt_add_virtio(Aml *scope,
}
}
+static void acpi_dsdt_add_pci(Aml *scope, MicrovmMachineState *mms)
+{
+ if (mms->pcie != ON_OFF_AUTO_ON) {
+ return;
+ }
+
+ acpi_dsdt_add_gpex(scope, &mms->gpex);
+}
+
static void
build_dsdt_microvm(GArray *table_data, BIOSLinker *linker,
MicrovmMachineState *mms)
@@ -112,6 +123,7 @@ build_dsdt_microvm(GArray *table_data, BIOSLinker *linker,
GED_MMIO_IRQ, AML_SYSTEM_MEMORY, GED_MMIO_BASE);
acpi_dsdt_add_power_button(sb_scope);
acpi_dsdt_add_virtio(sb_scope, mms);
+ acpi_dsdt_add_pci(sb_scope, mms);
aml_append(dsdt, sb_scope);
/* ACPI 5.0: Table 7-209 System State Package */
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index aedcae3426..73a7a142b4 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -46,6 +46,7 @@
#include "hw/virtio/virtio-mmio.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/generic_event_device.h"
+#include "hw/pci-host/gpex.h"
#include "cpu.h"
#include "elf.h"
@@ -101,6 +102,55 @@ static void microvm_gsi_handler(void *opaque, int n, int level)
qemu_set_irq(s->ioapic_irq[n], level);
}
+static void create_gpex(MicrovmMachineState *mms)
+{
+ X86MachineState *x86ms = X86_MACHINE(mms);
+ MemoryRegion *mmio32_alias;
+ MemoryRegion *mmio64_alias;
+ MemoryRegion *mmio_reg;
+ MemoryRegion *ecam_alias;
+ MemoryRegion *ecam_reg;
+ DeviceState *dev;
+ int i;
+
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ /* Map only the first size_ecam bytes of ECAM space */
+ ecam_alias = g_new0(MemoryRegion, 1);
+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
+ ecam_reg, 0, mms->gpex.ecam.size);
+ memory_region_add_subregion(get_system_memory(),
+ mms->gpex.ecam.base, ecam_alias);
+
+ /* Map the MMIO window into system address space so as to expose
+ * the section of PCI MMIO space which starts at the same base address
+ * (ie 1:1 mapping for that part of PCI MMIO space visible through
+ * the window).
+ */
+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+ if (mms->gpex.mmio32.size) {
+ mmio32_alias = g_new0(MemoryRegion, 1);
+ memory_region_init_alias(mmio32_alias, OBJECT(dev), "pcie-mmio32", mmio_reg,
+ mms->gpex.mmio32.base, mms->gpex.mmio32.size);
+ memory_region_add_subregion(get_system_memory(),
+ mms->gpex.mmio32.base, mmio32_alias);
+ }
+ if (mms->gpex.mmio64.size) {
+ mmio64_alias = g_new0(MemoryRegion, 1);
+ memory_region_init_alias(mmio64_alias, OBJECT(dev), "pcie-mmio64", mmio_reg,
+ mms->gpex.mmio64.base, mms->gpex.mmio64.size);
+ memory_region_add_subregion(get_system_memory(),
+ mms->gpex.mmio64.base, mmio64_alias);
+ }
+
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
+ x86ms->gsi[mms->gpex.irq + i]);
+ }
+}
+
static void microvm_devices_init(MicrovmMachineState *mms)
{
X86MachineState *x86ms = X86_MACHINE(mms);
@@ -147,6 +197,21 @@ static void microvm_devices_init(MicrovmMachineState *mms)
x86ms->acpi_dev = HOTPLUG_HANDLER(dev);
}
+ if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) {
+ /* use topmost 25% of the address space available */
+ hwaddr phys_size = (hwaddr)1 << X86_CPU(first_cpu)->phys_bits;
+ if (phys_size > 0x1000000ll) {
+ mms->gpex.mmio64.size = phys_size / 4;
+ mms->gpex.mmio64.base = phys_size - mms->gpex.mmio64.size;
+ }
+ mms->gpex.mmio32.base = PCIE_MMIO_BASE;
+ mms->gpex.mmio32.size = PCIE_MMIO_SIZE;
+ mms->gpex.ecam.base = PCIE_ECAM_BASE;
+ mms->gpex.ecam.size = PCIE_ECAM_SIZE;
+ mms->gpex.irq = PCIE_IRQ_BASE;
+ create_gpex(mms);
+ }
+
if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
qemu_irq *i8259;
@@ -324,6 +389,9 @@ static void microvm_fix_kernel_cmdline(MachineState *machine)
static void microvm_device_pre_plug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
+ X86CPU *cpu = X86_CPU(dev);
+
+ cpu->host_phys_bits = true; /* need reliable phys-bits */
x86_cpu_pre_plug(hotplug_dev, dev, errp);
}
@@ -446,6 +514,23 @@ static void microvm_machine_set_rtc(Object *obj, Visitor *v, const char *name,
visit_type_OnOffAuto(v, name, &mms->rtc, errp);
}
+static void microvm_machine_get_pcie(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+ OnOffAuto pcie = mms->pcie;
+
+ visit_type_OnOffAuto(v, name, &pcie, errp);
+}
+
+static void microvm_machine_set_pcie(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ visit_type_OnOffAuto(v, name, &mms->pcie, errp);
+}
+
static bool microvm_machine_get_isa_serial(Object *obj, Error **errp)
{
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
@@ -521,6 +606,7 @@ static void microvm_machine_initfn(Object *obj)
mms->pic = ON_OFF_AUTO_AUTO;
mms->pit = ON_OFF_AUTO_AUTO;
mms->rtc = ON_OFF_AUTO_AUTO;
+ mms->pcie = ON_OFF_AUTO_AUTO;
mms->isa_serial = true;
mms->option_roms = true;
mms->auto_kernel_cmdline = true;
@@ -587,6 +673,13 @@ static void microvm_class_init(ObjectClass *oc, void *data)
object_class_property_set_description(oc, MICROVM_MACHINE_RTC,
"Enable MC146818 RTC");
+ object_class_property_add(oc, MICROVM_MACHINE_PCIE, "OnOffAuto",
+ microvm_machine_get_pcie,
+ microvm_machine_set_pcie,
+ NULL, NULL);
+ object_class_property_set_description(oc, MICROVM_MACHINE_PCIE,
+ "Enable PCIe");
+
object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL,
microvm_machine_get_isa_serial,
microvm_machine_set_isa_serial);