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authorPeter Maydell2015-03-09 10:14:28 +0100
committerPeter Maydell2015-03-09 10:14:28 +0100
commit0048fa6c807fc8fb5c52873562ea3debfa65f085 (patch)
tree1b0e846afaf7787006e5dd535e437e5874b5f90a /hw/ide/ich.c
parentMerge remote-tracking branch 'remotes/xtensa/tags/20150307-xtensa' into staging (diff)
parentacpi: drop unused code (diff)
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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
pci, pc, virtio fixes and cleanups A bunch of fixes all over the place. All of ACPI refactoring has been merged. Legacy pci commands have been dropped. virtio header cleanup initial patches from virtio-1.0 branch Signed-off-by: Michael S. Tsirkin <mst@redhat.com> * remotes/mst/tags/for_upstream: (130 commits) acpi: drop unused code aml-build: comment fix acpi-build: fix typo in comment acpi: update generated files vhost user:support vhost user nic for non msi guests aml-build: fix build for glib < 2.22 acpi: update generated files Makefile.target: binary depends on config-devices acpi-test-data: update after pci rewrite acpi, mem-hotplug: use PC_DIMM_SLOT_PROP in acpi_memory_plug_cb(). pci-hotplug-old: Has been dead for five major releases, bury pci: Give a few helpers internal linkage acpi: make build_*() routines static to aml-build.c pc: acpi: remove not used anymore ssdt-[misc|pcihp].hex.generated blobs pc: acpi-build: drop template patching and create PCI bus tree dynamically tests: ACPI: update pc/SSDT.bridge due to new alg of PCI tree creation pc: acpi-build: simplify PCI bus tree generation tests: add ACPI blobs for qemu with bridge cases tests: bios-tables-test: add support for testing bridges tests: ACPI test blobs update due to PCI0._CRS changes ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Conflicts: hw/pci/pci-hotplug-old.c
Diffstat (limited to 'hw/ide/ich.c')
-rw-r--r--hw/ide/ich.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index fb1d095503..b1d8874671 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -98,7 +98,7 @@ static void pci_ich9_reset(DeviceState *dev)
ahci_reset(&d->ahci);
}
-static int pci_ich9_ahci_init(PCIDevice *dev)
+static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
{
struct AHCIPCIState *d;
int sata_cap_offset;
@@ -123,10 +123,11 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
&d->ahci.mem);
- sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
- ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE);
+ sata_cap_offset = pci_add_capability2(dev, PCI_CAP_ID_SATA,
+ ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE,
+ errp);
if (sata_cap_offset < 0) {
- return sata_cap_offset;
+ return;
}
sata_cap = dev->config + sata_cap_offset;
@@ -139,8 +140,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
* should be PMCAP, the Intel ICH9 data sheet specifies that the ICH9
* AHCI device puts the MSI capability first, pointing to 0x80. */
msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false);
-
- return 0;
}
static void pci_ich9_uninit(PCIDevice *dev)
@@ -158,7 +157,7 @@ static void ich_ahci_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->init = pci_ich9_ahci_init;
+ k->realize = pci_ich9_ahci_realize;
k->exit = pci_ich9_uninit;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82801IR;