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author | Peter Maydell | 2022-04-08 16:15:32 +0200 |
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committer | Peter Maydell | 2022-04-22 15:44:52 +0200 |
commit | 641be69745c49d3c35efb62ee41d21d701b210ba (patch) | |
tree | 3ab42b0ff9e8bfe524b4ba1d00c1149231fc3127 /hw/intc/arm_gicv3_cpuif.c | |
parent | hw/intc/arm_gicv3: Implement GICv4's new redistributor frame (diff) | |
download | qemu-641be69745c49d3c35efb62ee41d21d701b210ba.tar.gz qemu-641be69745c49d3c35efb62ee41d21d701b210ba.tar.xz qemu-641be69745c49d3c35efb62ee41d21d701b210ba.zip |
hw/intc/arm_gicv3: Implement new GICv4 redistributor registers
Implement the new GICv4 redistributor registers: GICR_VPROPBASER
and GICR_VPENDBASER; for the moment we implement these as simple
reads-as-written stubs, together with the necessary migration
and reset handling.
We don't put ID-register checks on the handling of these registers,
because they are all in the only-in-v4 extra register frames, so
they're not accessible in a GICv3.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-24-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gicv3_cpuif.c')
0 files changed, 0 insertions, 0 deletions