diff options
| author | Jeff Kubascik | 2020-01-17 15:09:31 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-01-17 15:27:16 +0100 |
| commit | ef1255212a721e3ebc2be4bec9426bda9d2ee308 (patch) | |
| tree | dc81d499d8b605c8fbc8178acd0516478c3ed56c /hw/intc/arm_gicv3_cpuif.c | |
| parent | target/arm: adjust program counter for wfi exception in AArch32 (diff) | |
| download | qemu-ef1255212a721e3ebc2be4bec9426bda9d2ee308.tar.gz qemu-ef1255212a721e3ebc2be4bec9426bda9d2ee308.tar.xz qemu-ef1255212a721e3ebc2be4bec9426bda9d2ee308.zip | |
arm/gicv3: update virtual irq state after IAR register read
The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the
register activates the highest priority pending interrupt and provides its
interrupt ID. Activating an interrupt can change the CPU's virtual interrupt
state - this change makes sure the virtual irq state is updated.
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gicv3_cpuif.c')
| -rw-r--r-- | hw/intc/arm_gicv3_cpuif.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index a254b0ce87..08e000e33c 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -664,6 +664,9 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), intid); + + gicv3_cpuif_virt_update(cs); + return intid; } |