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| author | Peter Maydell | 2019-05-24 14:42:47 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-06-17 16:13:19 +0200 |
| commit | e40f60730a208338057d51bfc6c98f89af8eab2d (patch) | |
| tree | 69db5809154d9d2c04e65db07e6612ae8f67da90 /hw/intc/arm_gicv3_dist.c | |
| parent | hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards (diff) | |
| download | qemu-e40f60730a208338057d51bfc6c98f89af8eab2d.tar.gz qemu-e40f60730a208338057d51bfc6c98f89af8eab2d.tar.xz qemu-e40f60730a208338057d51bfc6c98f89af8eab2d.zip | |
hw/intc/arm_gicv3: Fix decoding of ID register range
The GIC ID registers cover an area 0x30 bytes in size
(12 registers, 4 bytes each). We were incorrectly decoding
only the first 0x20 bytes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190524124248.28394-2-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gicv3_dist.c')
| -rw-r--r-- | hw/intc/arm_gicv3_dist.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 53c55c5729..e6fe4905fd 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -533,7 +533,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, } return MEMTX_OK; } - case GICD_IDREGS ... GICD_IDREGS + 0x1f: + case GICD_IDREGS ... GICD_IDREGS + 0x2f: /* ID registers */ *data = gicv3_idreg(offset - GICD_IDREGS); return MEMTX_OK; @@ -744,7 +744,7 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr offset, gicd_write_irouter(s, attrs, irq, r); return MEMTX_OK; } - case GICD_IDREGS ... GICD_IDREGS + 0x1f: + case GICD_IDREGS ... GICD_IDREGS + 0x2f: case GICD_TYPER: case GICD_IIDR: /* RO registers, ignore the write */ |