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| author | Peter Maydell | 2022-04-08 16:15:13 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-04-22 10:19:24 +0200 |
| commit | 50a3a309e12789e28a3c4e260348ed7305c28b99 (patch) | |
| tree | 4e16a119a46832bbbdd24f44225a74f4b1255b25 /hw/intc/arm_gicv3_its.c | |
| parent | hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count (diff) | |
| download | qemu-50a3a309e12789e28a3c4e260348ed7305c28b99.tar.gz qemu-50a3a309e12789e28a3c4e260348ed7305c28b99.tar.xz qemu-50a3a309e12789e28a3c4e260348ed7305c28b99.zip | |
hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers
We use the common function gicv3_idreg() to supply the CoreSight ID
register values for the GICv3 for the copies of these ID registers in
the distributor, redistributor and ITS register frames. This isn't
quite correct, because while most of the register values are the
same, the PIDR0 value should vary to indicate which of these three
frames it is. (You can see this and also the correct values of these
PIDR0 registers by looking at the GIC-600 or GIC-700 TRMs, for
example.)
Make gicv3_idreg() take an extra argument for the PIDR0 value.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-5-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gicv3_its.c')
| -rw-r--r-- | hw/intc/arm_gicv3_its.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 44914f2578..f8467b61ec 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1161,7 +1161,7 @@ static bool its_readl(GICv3ITSState *s, hwaddr offset, break; case GITS_IDREGS ... GITS_IDREGS + 0x2f: /* ID registers */ - *data = gicv3_idreg(offset - GITS_IDREGS); + *data = gicv3_idreg(offset - GITS_IDREGS, GICV3_PIDR0_ITS); break; case GITS_TYPER: *data = extract64(s->typer, 0, 32); |