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| author | Peter Maydell | 2022-05-12 17:14:53 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-05-19 17:19:02 +0200 |
| commit | 9c6f933e71ccfde036d7e19c1ddc2b1a82cc45c0 (patch) | |
| tree | c6c17062fef12afc84b4a79f617c1ab04cb18c4f /hw/intc/arm_gicv3_kvm.c | |
| parent | hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters (diff) | |
| download | qemu-9c6f933e71ccfde036d7e19c1ddc2b1a82cc45c0.tar.gz qemu-9c6f933e71ccfde036d7e19c1ddc2b1a82cc45c0.tar.xz qemu-9c6f933e71ccfde036d7e19c1ddc2b1a82cc45c0.zip | |
hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1
As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
virtual priority bit setting, not the physical priority bit setting.
(For QEMU currently we always implement 8 bits of physical priority,
so the PRIbits field was previously 7, since it is defined to be
"priority bits - 1".)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-3-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-2-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gicv3_kvm.c')
0 files changed, 0 insertions, 0 deletions