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| author | Peter Maydell | 2017-10-11 19:24:36 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-10-12 14:24:39 +0200 |
| commit | a94bb9cd586c50d13b68e5fa4628cc36e29805c4 (patch) | |
| tree | 3ce433866e06d163514d7f7030b4fa1c6369fe2d /hw/intc/armv7m_nvic.c | |
| parent | target/arm: Implement SG instruction corner cases (diff) | |
| download | qemu-a94bb9cd586c50d13b68e5fa4628cc36e29805c4.tar.gz qemu-a94bb9cd586c50d13b68e5fa4628cc36e29805c4.tar.xz qemu-a94bb9cd586c50d13b68e5fa4628cc36e29805c4.zip | |
nvic: Add missing 'break'
Coverity points out that we forgot the 'break' for
the SAU_CTRL write case (CID1381683). This has
no actual visible consequences because it happens
that the following case is effectively a no-op.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1507742676-9908-1-git-send-email-peter.maydell@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/intc/armv7m_nvic.c')
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 22d5e6e6af..a42961c643 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1447,6 +1447,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, return; } cpu->env.sau.ctrl = value & 3; + break; case 0xdd4: /* SAU_TYPE */ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { goto bad_offset; |