diff options
| author | Peter Maydell | 2017-09-07 14:54:53 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-09-07 14:54:53 +0200 |
| commit | ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9 (patch) | |
| tree | 56930bb977234b0836ed9e57fba0622a1facd3d3 /hw/intc/armv7m_nvic.c | |
| parent | target/arm: Make MPU_RNR register banked for v8M (diff) | |
| download | qemu-ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9.tar.gz qemu-ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9.tar.xz qemu-ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9.zip | |
target/arm: Make MPU_CTRL register banked for v8M
Make the MPU_CTRL register banked if v8M security extensions are
enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/armv7m_nvic.c')
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c3c214c22c..a4c298f9c9 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -541,7 +541,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) return cpu->pmsav7_dregion << 8; break; case 0xd94: /* MPU_CTRL */ - return cpu->env.v7m.mpu_ctrl; + return cpu->env.v7m.mpu_ctrl[attrs.secure]; case 0xd98: /* MPU_RNR */ return cpu->env.pmsav7.rnr[attrs.secure]; case 0xd9c: /* MPU_RBAR */ @@ -720,9 +720,10 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " "UNPREDICTABLE\n"); } - cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK | - R_V7M_MPU_CTRL_HFNMIENA_MASK | - R_V7M_MPU_CTRL_PRIVDEFENA_MASK); + cpu->env.v7m.mpu_ctrl[attrs.secure] + = value & (R_V7M_MPU_CTRL_ENABLE_MASK | + R_V7M_MPU_CTRL_HFNMIENA_MASK | + R_V7M_MPU_CTRL_PRIVDEFENA_MASK); tlb_flush(CPU(cpu)); break; case 0xd98: /* MPU_RNR */ |