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| author | Will Newton | 2014-01-29 11:31:51 +0100 |
|---|---|---|
| committer | Peter Maydell | 2014-02-08 15:47:28 +0100 |
| commit | 239c20c7c87816402acdb118a5295acda9d25c5c (patch) | |
| tree | b3accf3d2b4dd37233829b9d177ac2ee84c6ed16 /hw/intc/gic_internal.h | |
| parent | target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group (diff) | |
| download | qemu-239c20c7c87816402acdb118a5295acda9d25c5c.tar.gz qemu-239c20c7c87816402acdb118a5295acda9d25c5c.tar.xz qemu-239c20c7c87816402acdb118a5295acda9d25c5c.zip | |
target-arm: Add support for AArch32 64bit VCVTB and VCVTT
Add support for the AArch32 floating-point half-precision to double-
precision conversion VCVTB and VCVTT instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>
[PMM: fixed a minor missing-braces style issue]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/gic_internal.h')
0 files changed, 0 insertions, 0 deletions