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| author | Fabian Aggeler | 2015-05-12 12:57:17 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-05-12 12:57:17 +0200 |
| commit | 32951860834f09d1c1a0b81d8d7d5529e2d0e074 (patch) | |
| tree | 2056b5bdb2eb8a02e338dbb5ddc3f47267964725 /hw/intc/gic_internal.h | |
| parent | hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked (diff) | |
| download | qemu-32951860834f09d1c1a0b81d8d7d5529e2d0e074.tar.gz qemu-32951860834f09d1c1a0b81d8d7d5529e2d0e074.tar.xz qemu-32951860834f09d1c1a0b81d8d7d5529e2d0e074.zip | |
hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked
ICCICR/GICC_CTLR is banked in GICv1 implementations with Security
Extensions or in GICv2 in independent from Security Extensions.
This makes it possible to enable forwarding of interrupts from
the CPU interfaces to the connected processors for Group0 and Group1.
We also allow to set additional bits like AckCtl and FIQEn by changing
the type from bool to uint32. Since the field does not only store the
enable bit anymore and since we are touching the vmstate, we use the
opportunity to rename the field to cpu_ctlr.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1430502643-25909-9-git-send-email-peter.maydell@linaro.org
Message-id: 1429113742-8371-9-git-send-email-greg.bellows@linaro.org
[PMM: rewrote to store state in a single uint32_t rather than
keeping the NS and S banked variants separate; this considerably
simplifies the get/set functions]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/gic_internal.h')
| -rw-r--r-- | hw/intc/gic_internal.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 3b4b3fbc0e..81c764c100 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -57,6 +57,22 @@ #define GICD_CTLR_EN_GRP0 (1U << 0) #define GICD_CTLR_EN_GRP1 (1U << 1) +#define GICC_CTLR_EN_GRP0 (1U << 0) +#define GICC_CTLR_EN_GRP1 (1U << 1) +#define GICC_CTLR_ACK_CTL (1U << 2) +#define GICC_CTLR_FIQ_EN (1U << 3) +#define GICC_CTLR_CBPR (1U << 4) /* GICv1: SBPR */ +#define GICC_CTLR_EOIMODE (1U << 9) +#define GICC_CTLR_EOIMODE_NS (1U << 10) + +/* Valid bits for GICC_CTLR for GICv1, v1 with security extensions, + * GICv2 and GICv2 with security extensions: + */ +#define GICC_CTLR_V1_MASK 0x1 +#define GICC_CTLR_V1_S_MASK 0x1f +#define GICC_CTLR_V2_MASK 0x21f +#define GICC_CTLR_V2_S_MASK 0x61f + /* The special cases for the revision property: */ #define REV_11MPCORE 0 #define REV_NVIC 0xffffffff |