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| author | Michael Davidsaver | 2017-02-28 13:08:17 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-02-28 13:08:17 +0100 |
| commit | 7c14b3ac072c48614ca888e101d17ee64312c89f (patch) | |
| tree | f2665dee1c08714dc2bff2c6ec35fc93f28f50da /hw/intc/gic_internal.h | |
| parent | armv7m: Fix condition check for taking exceptions (diff) | |
| download | qemu-7c14b3ac072c48614ca888e101d17ee64312c89f.tar.gz qemu-7c14b3ac072c48614ca888e101d17ee64312c89f.tar.xz qemu-7c14b3ac072c48614ca888e101d17ee64312c89f.zip | |
arm: gic: Remove references to NVIC
Now that the NVIC is its own separate implementation, we can
clean up the GIC code by removing REV_NVIC and conditionals
which use it.
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Diffstat (limited to 'hw/intc/gic_internal.h')
| -rw-r--r-- | hw/intc/gic_internal.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 3f311740da..7fe87b13de 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -25,9 +25,7 @@ #define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1))) -/* The NVIC has 16 internal vectors. However these are not exposed - through the normal GIC interface. */ -#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0) +#define GIC_BASE_IRQ 0 #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm) #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm) @@ -75,7 +73,6 @@ /* The special cases for the revision property: */ #define REV_11MPCORE 0 -#define REV_NVIC 0xffffffff void gic_set_pending_private(GICState *s, int cpu, int irq); uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs); @@ -87,7 +84,7 @@ void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, static inline bool gic_test_pending(GICState *s, int irq, int cm) { - if (s->revision == REV_NVIC || s->revision == REV_11MPCORE) { + if (s->revision == REV_11MPCORE) { return s->irq_state[irq].pending & cm; } else { /* Edge-triggered interrupts are marked pending on a rising edge, but |