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| author | Fabian Aggeler | 2015-05-12 12:57:17 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-05-12 12:57:17 +0200 |
| commit | 8150847061f8d2606101bfff77cc6ec86b081ab0 (patch) | |
| tree | 8447b726a34d0a104d2282145e3eb3f004f6b3d2 /hw/intc/gic_internal.h | |
| parent | hw/intc/arm_gic: Implement Non-secure view of RPR (diff) | |
| download | qemu-8150847061f8d2606101bfff77cc6ec86b081ab0.tar.gz qemu-8150847061f8d2606101bfff77cc6ec86b081ab0.tar.xz qemu-8150847061f8d2606101bfff77cc6ec86b081ab0.zip | |
hw/intc/arm_gic: Restrict priority view
GICs with Security Extensions restrict the non-secure view of the
interrupt priority and priority mask registers.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1430502643-25909-11-git-send-email-peter.maydell@linaro.org
Message-id: 1429113742-8371-15-git-send-email-greg.bellows@linaro.org
[PMM: minor code tweaks; fixed missing masking in gic_set_priority_mask
and gic_set_priority]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/gic_internal.h')
| -rw-r--r-- | hw/intc/gic_internal.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 81c764c100..119fb8147e 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -82,7 +82,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu); void gic_complete_irq(GICState *s, int cpu, int irq); void gic_update(GICState *s); void gic_init_irqs_and_distributor(GICState *s); -void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, + MemTxAttrs attrs); static inline bool gic_test_pending(GICState *s, int irq, int cm) { |