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| author | Joe Komlodi | 2020-11-17 00:11:04 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-15 14:39:30 +0100 |
| commit | 23af268566069183285bebbdf95b1b37cb7c0942 (patch) | |
| tree | e5b1da75efa6048413e01e45df22b6c66a8794cb /hw/intc/gicv3_internal.h | |
| parent | hw/block/m25p80: Check SPI mode before running some Numonyx commands (diff) | |
| download | qemu-23af268566069183285bebbdf95b1b37cb7c0942.tar.gz qemu-23af268566069183285bebbdf95b1b37cb7c0942.tar.xz qemu-23af268566069183285bebbdf95b1b37cb7c0942.zip | |
hw/block/m25p80: Fix Numonyx fast read dummy cycle count
Numonyx chips determine the number of cycles to wait based on bits 7:4
in the volatile configuration register.
However, if these bits are 0x0 or 0xF, the number of dummy cycles to
wait is 10 for QIOR and QIOR4 commands or when in QIO mode, and otherwise 8 for
the currently supported fast read commands. [1]
[1]
https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf?rev=9b167fbf2b3645efba6385949a72e453
Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Message-id: 1605568264-26376-5-git-send-email-komlodi@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/gicv3_internal.h')
0 files changed, 0 insertions, 0 deletions