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| author | Jim Shu | 2022-10-03 06:14:40 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-10-14 06:29:50 +0200 |
| commit | 1aae4a12dab4bf1adc249c2ac6178d15e4b5a77d (patch) | |
| tree | ddd3df4d49986b9b3dd2c5d294a92f8ac42e2a25 /hw/intc/imx_gpcv2.c | |
| parent | hw/intc: sifive_plic: fix hard-coded max priority level (diff) | |
| download | qemu-1aae4a12dab4bf1adc249c2ac6178d15e4b5a77d.tar.gz qemu-1aae4a12dab4bf1adc249c2ac6178d15e4b5a77d.tar.xz qemu-1aae4a12dab4bf1adc249c2ac6178d15e4b5a77d.zip | |
hw/intc: sifive_plic: change interrupt priority register to WARL field
PLIC spec [1] requires interrupt source priority registers are WARL
field and the number of supported priority is power-of-2 to simplify SW
discovery.
Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC
spec, whose number of supported priority is not power-of-2. Just change
each bit of interrupt priority register to WARL field when the number of
supported priority is power-of-2.
[1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Clément Chigot <chigot@adacore.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221003041440.2320-3-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/imx_gpcv2.c')
0 files changed, 0 insertions, 0 deletions