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| author | Paul Burton | 2016-09-08 16:51:53 +0200 |
|---|---|---|
| committer | Yongbok Kim | 2017-02-21 23:24:58 +0100 |
| commit | 2e2a1b4648114ebbb371c10f31c66d10bcd40051 (patch) | |
| tree | 0625e4b740604fdfd07146f601adf504e50c1e9a /hw/intc/intc.c | |
| parent | hw/mips_gictimer: provide API for retrieving frequency (diff) | |
| download | qemu-2e2a1b4648114ebbb371c10f31c66d10bcd40051.tar.gz qemu-2e2a1b4648114ebbb371c10f31c66d10bcd40051.tar.xz qemu-2e2a1b4648114ebbb371c10f31c66d10bcd40051.zip | |
hw/mips_gic: Update pin state on mask changes
If the GIC interrupt mask is changed by a write to the smask (set mask)
or rmask (reset mask) registers, we need to re-evaluate the state of the
pins/IRQs fed to the CPU. Without doing so we risk leaving a pin high
despite the interrupt that led to that state being masked, or losing
interrupts if an already pending interrupt is unmasked.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'hw/intc/intc.c')
0 files changed, 0 insertions, 0 deletions