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| author | Peter Maydell | 2017-01-20 12:15:10 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-01-20 12:15:10 +0100 |
| commit | df313f481f4167bf0af0a0d362b77aa22574ff56 (patch) | |
| tree | ce7409ed350f1cacff06806cbc1a9bf169d7b399 /hw/intc/trace-events | |
| parent | hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors (diff) | |
| download | qemu-df313f481f4167bf0af0a0d362b77aa22574ff56.tar.gz qemu-df313f481f4167bf0af0a0d362b77aa22574ff56.tar.xz qemu-df313f481f4167bf0af0a0d362b77aa22574ff56.zip | |
hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers
Implement the the ICV_ registers HPPIR, DIR and RPR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1483977924-14522-11-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/trace-events')
| -rw-r--r-- | hw/intc/trace-events | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 19fe1d580a..fc9ec576a6 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -133,6 +133,9 @@ gicv3_icv_igrpen_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IGRPEN%d r gicv3_icv_igrpen_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IGRPEN%d write cpu %x value 0x%" PRIx64 gicv3_icv_ctlr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR read cpu %x value 0x%" PRIx64 gicv3_icv_ctlr_write(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR write cpu %x value 0x%" PRIx64 +gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_RPR read cpu %x value 0x%" PRIx64 +gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR%d read cpu %x value 0x%" PRIx64 +gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu %x value 0x%" PRIx64 # hw/intc/arm_gicv3_dist.c gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" |