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| author | Jim Shu | 2022-10-03 06:14:39 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-10-14 06:29:50 +0200 |
| commit | 55144a1fd0d1f37b49ea051291decbbe427b7714 (patch) | |
| tree | 9843c9302248ba7960a9191c3b43a6a2c9912575 /hw/intc/xilinx_intc.c | |
| parent | disas/riscv.c: rvv: Add disas support for vector instructions (diff) | |
| download | qemu-55144a1fd0d1f37b49ea051291decbbe427b7714.tar.gz qemu-55144a1fd0d1f37b49ea051291decbbe427b7714.tar.xz qemu-55144a1fd0d1f37b49ea051291decbbe427b7714.zip | |
hw/intc: sifive_plic: fix hard-coded max priority level
The maximum priority level is hard-coded when writing to interrupt
priority register. However, when writing to priority threshold register,
the maximum priority level is from num_priorities Property which is
configured by platform.
Also change interrupt priority register to use num_priorities Property
in maximum priority level.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221003041440.2320-2-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/xilinx_intc.c')
0 files changed, 0 insertions, 0 deletions