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| author | Cédric Le Goater | 2018-06-06 09:33:53 +0200 |
|---|---|---|
| committer | David Gibson | 2018-06-12 02:44:36 +0200 |
| commit | c8fd8373e42821984400382cd91b8bf4e7c14e3b (patch) | |
| tree | 429581c1c7425f21eb676092f9348b971513471a /hw/lm32 | |
| parent | mos6522: convert VMSTATE_TIMER_PTR_TEST to VMSTATE_TIMER_PTR (diff) | |
| download | qemu-c8fd8373e42821984400382cd91b8bf4e7c14e3b.tar.gz qemu-c8fd8373e42821984400382cd91b8bf4e7c14e3b.tar.xz qemu-c8fd8373e42821984400382cd91b8bf4e7c14e3b.zip | |
target/ppc: extend eieio for POWER9
POWER9 introduced a new variant of the eieio instruction using bit 6
as a hint to tell the CPU it is a store-forwarding barrier.
The usage of this eieio extension was recently added in Linux 4.17
which activated the "support for a store forwarding barrier at kernel
entry/exit".
Unfortunately, it is not possible to insert this new eieio instruction
without considerable change in ppc_tr_translate_insn(). So instead we
loosen the QEMU eieio instruction mask and modify the gen_eieio()
helper to test for bit6. On non-POWER9 CPUs, the bit6 is just ignored
but a warning is emitted as this is not an instruction software should
be using.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/lm32')
0 files changed, 0 insertions, 0 deletions